| US 7,456,481 B2 | ||
| Semiconductor device and manufacturing method of the same | ||
| Satoshi Inaba, Yokohama (Japan); and Makoto Fujiwara, Yokohama (Japan) | ||
| Assigned to Kabushiki Kaisha Toshiba, Tokyo (Japan) | ||
| Filed on Aug. 01, 2006, as Appl. No. 11/496,452. | ||
| Application 11/496452 is a division of application No. 10/799780, filed on Mar. 15, 2004, granted, now 7,112,858. | ||
| Claims priority of application No. 2003-352628 (JP), filed on Oct. 10, 2003. | ||
| Prior Publication US 2006/0267112 A1, Nov. 30, 2006 | ||
| Int. Cl. H01L 29/76 (2006.01) | ||
| U.S. Cl. 257—401 [257/204; 257/250; 257/E27.098; 438/284] | 10 Claims |
| 1. A semiconductor device, comprising:
a first device region including a plurality of source regions and a plurality of drain regions of first conductivity type
transistors;
a plurality of loop-shaped gate electrode regions of the first conductivity type transistors, each of the gate electrode regions
formed on the first device region;
a second device region including a plurality of source regions and a plurality of drain regions of a second conductivity type
transistors;
a plurality of loop-shaped gate electrode regions of the second conductivity type transistors, each of the gate electrode
regions formed on the second device region and electrically coupled to each of the gate electrode regions of the first conductivity
type transistors;
a first wiring configured to supply a first voltage to at least one of the source regions of the first device region;
a second wiring configured to supply a second voltage to at least one of the source regions of the second device region; and
a third wiring electrically coupled to the drain regions of the first and second device regions and to the gate electrode
regions of the first and the second conductivity type transistors;
wherein the plurality of the loop-shaped gate electrode regions of the first conductivity type transistors are arranged to
surround a part of the first device region and at least one device isolation region, and
wherein the plurality of the loop-shaped gate electrode regions of the second conductivity type transistors are arranged to
surround a part of the second device region and at least one device isolation region.
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