| US 7,456,480 B2 | ||
| Semiconductor device | ||
| Hiroshi Watanabe, Yokohama (Japan) | ||
| Assigned to Kabushiki Kaisha Toshiba, Tokyo (Japan) | ||
| Filed on Jun. 17, 2005, as Appl. No. 11/154,628. | ||
| Claims priority of application No. 2004-282058 (JP), filed on Sep. 28, 2004. | ||
| Prior Publication US 2006/0087360 A1, Apr. 27, 2006 | ||
| Int. Cl. H01L 27/088 (2006.01) | ||
| U.S. Cl. 257—393 [257/E45.002] | 11 Claims |
| 1. A semiconductor device comprising:
an input terminal;
a first aging device comprising a first source, a first drain, and a first gate, the first source being connected to the input
terminal in such a manner as to turn on at a first life τ1 and turn off at a second life τ2 (>τ1);
a second aging device comprising a second source, a second drain, and a second gate, the second source being connected to
the input terminal, the second gate being connected to the first drain of the first aging device, the second drain being connected
to the first gate of the first aging device in such a manner as to turn on at a third life τ3 and turn off at a fourth life τ4 (>τ3);
a first switch element comprising a first terminal and a second terminal, the first terminal being connected to the first
drain of the first aging device in such a manner as to turn off when the second aging device is on;
a second switch element comprising a third terminal and a fourth terminal, the third terminal being connected to the second
drain of the second aging device in such a manner as to turn off when the first aging device is on; and
an output terminal connected to the second terminal of the first switch element, and the fourth terminal of the second switch
element.
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