| US 7,456,476 B2 | ||
| Nonplanar semiconductor device with partially or fully wrapped around gate electrode and methods of fabrication | ||
| Scott A. Hareland, Tigard, Oreg. (US); Robert S. Chau, Beaverton, Oreg. (US); Brian S. Doyle, Portland, Oreg. (US); Rafael Rios, Portland, Oreg. (US); Tom Linton, San Jose, Calif. (US); and Suman Datta, Beaverton, Oreg. (US) | ||
| Assigned to Intel Corporation, Santa Clara, Calif. (US) | ||
| Filed on Jun. 27, 2003, as Appl. No. 10/607,769. | ||
| Prior Publication US 2006/0172497 A1, Aug. 03, 2006 | ||
| Int. Cl. H01L 29/786 (2006.01) | ||
| U.S. Cl. 257—349 [438/284; 257/E29.242; 257/E29.273] | 12 Claims |
| 1. A nonplanar semiconductor device comprising:
a semiconductor body having a top surface opposite a bottom surface formed above an insulating substrate, wherein said semiconductor
body has a pair of laterally opposite sidewalls;
a gate dielectric formed on said top surface of said semiconductor body, on only a portion of said bottom surface of said
semiconductor body, and on said laterally opposite sidewalls of said semiconductor body;
a gate electrode formed on said gate dielectric on said top surface of said semiconductor body, adjacent to said gate dielectric
on said laterally opposite sidewalls of said semiconductor body, and beneath said gate dielectric on said portion of said
bottom surface of said semiconductor body, wherein said gate electrode has a pair of laterally opposite sidewalls oriented
perpendicularly to said laterally opposite sidewalls of said semiconductor body, said gate electrode having a top portion
and a bottom portion, and wherein said bottom portion of said gate electrode undercuts said top portion of said gate electrode
along said pair of laterally opposite sidewalls of said gate electrode; and
a pair of source/drain regions formed in said semiconductor body on opposite sides of said gate electrode.
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