| US 7,456,472 B2 | ||
| Semiconductor device and manufacturing method thereof | ||
| Satoshi Inaba, Yokohama (Japan) | ||
| Assigned to Kabushiki Kaisha Toshiba, Tokyo (Japan) | ||
| Filed on Dec. 07, 2004, as Appl. No. 11/5,477. | ||
| Claims priority of application No. 2004-287702 (JP), filed on Sep. 30, 2004. | ||
| Prior Publication US 2006/0073647 A1, Apr. 06, 2006 | ||
| Int. Cl. H01L 29/76 (2006.01) | ||
| U.S. Cl. 257—341 [257/382] | 18 Claims |
| 1. A semiconductor device comprising:
a source region and a drain region disposed on a semiconductor substrate;
a plurality of fins which interconnect the source region and the drain region;
a plurality of first gate electrodes, each first gate electrode disposed on the semiconductor substrate and to one side face
of each fin;
a plurality of second gate electrodes, each second gate electrode disposed on the semiconductor substrate and to the other
side face of the fin to face a respective of the first gate electrodes with respect to the fin, and separated from the first
gate electrodes;
a plurality of first pad electrodes connected to respective of the first gate electrodes;
a first wiring which interconnects the plurality of first pad electrodes;
a plurality of second pad electrodes connected to respective of the second gate electrodes; and
a second wiring which interconnects the plurality of second pad electrodes.
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