| US 7,456,099 B2 | ||
| Method of forming a structure for reducing lateral fringe capacitance in semiconductor devices | ||
| Lawrence A. Clevenger, LaGrangeville, N.Y. (US); Stephan Grunow, Wappingers Falls, N.Y. (US); Kaushik A. Kumar, Beacon, N.Y. (US); Kevin S. Petrarca, Newburgh, N.Y. (US); Vidhya Ramachandran, Ossining, N.Y. (US); and Theodorus E. Standaert, Pine Bush, N.Y. (US) | ||
| Assigned to International Business Machines Corporation, Armonk, N.Y. (US) | ||
| Filed on May 25, 2006, as Appl. No. 11/420,253. | ||
| Prior Publication US 2007/0275552 A1, Nov. 29, 2007 | ||
| Int. Cl. H01L 21/4763 (2006.01); H01L 21/44 (2006.01) | ||
| U.S. Cl. 438—637 [438/671; 438/672; 438/675; 438/700; 438/717; 257/E21.231] | 8 Claims |
| 1. A method for forming a semiconductor structure, the method comprising:
defining a plurality of conductive lines within an interlevel dielectric (ILD) layer having a hardmask layer formed thereon;
recessing fill material of the conductive lines to a level below the top of said ILD layer;
forming a protective insulation layer over the top of said recessed fill material;
defining a domed pattern within said hardmask layer, and thereby removing said protective insulation layer;
removing said hardmask layer so as to transfer said domed pattern into the top of said ILD layer; and
forming a cap layer over said ILD layer and said conductive lines, wherein said cap layer takes the form of said domed pattern.
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