| US 7,456,068 B2 | ||
| Forming ultra-shallow junctions | ||
| Jack T. Kavalieros, Portland, Oreg. (US); Mark Y. Liu, Portland, Oreg. (US); and Suman Datta, Beaverton, Oreg. (US) | ||
| Assigned to Intel Corporation, Santa Clara, Calif. (US) | ||
| Filed on Jun. 08, 2006, as Appl. No. 11/449,972. | ||
| Prior Publication US 2007/0287259 A1, Dec. 13, 2007 | ||
| Int. Cl. H01L 21/336 (2006.01); H01L 21/4763 (2006.01) | ||
| U.S. Cl. 438—301 [438/303; 438/530; 438/585; 257/E21.634] | 15 Claims |
| 1. A method of forming a semiconductor structure comprising:
forming a first gate electrode above a substrate;
forming tip implant regions in said substrate, on either side of said first gate electrode;
annealing said tip implant regions with a laser anneal process;
forming a first pair of gate isolation spacers adjacent the sidewalls of said first gate electrode;
forming a second pair of gate isolation spacers adjacent the sidewalls of said first pair of gate isolation spacers;
removing said first gate electrode and said first pair of gate isolation spacers; and
forming a second gate electrode in between said second pair of gate isolation spacers, wherein the annealing said tip implant
regions is performed prior to forming said second gate electrode.
|