| US 7,456,062 B1 | ||
| Method of forming a semiconductor device | ||
| William G. En, Milpitas, Calif. (US); Thorsten Kammler, Ottendorf-Okrilla (Germany); Eric N. Paton, Morgan Hill, Calif. (US); Paul R. Besser, Sunnyvale, Calif. (US); and Simon Siu-Sing Chan, Saratoga, Calif. (US) | ||
| Assigned to Advanced Micro Devices, Inc., Sunnyvale, Calif. (US) | ||
| Filed on Aug. 23, 2005, as Appl. No. 11/209,871. | ||
| Application 11/209871 is a continuation in part of application No. 10/969774, filed on Oct. 20, 2004, abandoned. | ||
| Int. Cl. H01L 21/8238 (2006.01); H01L 21/336 (2006.01); H01L 21/3205 (2006.01); H01L 21/4763 (2006.01) | ||
| U.S. Cl. 438—231 [438/305; 438/586; 257/E21.148; 257/E21.151] | 21 Claims |
| 1. A method of manufacturing a semiconductor device, the method comprising:
forming a sidewall spacer structure adjacent to a sidewall of a conductive gate structure overlying a semiconductor substrate
at a transistor location, wherein the sidewall spacer structure comprises a first offset spacer containing nitrogen and a
second offset spacer between the first offset spacer and the conductive gate structure, the first offset spacer defining an
outer surface of the sidewall spacer structure;
implanting a source/drain extension dopant at a source/drain location of the transistor location subsequent to formation of
the second offset spacer and prior to formation of the first offset spacer; and
forming an epitaxial layer at a source/drain location of the transistor location, the epitaxial layer abutting the outer surface
of the sidewall spacer structure.
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