| US 7,454,450 B2 | ||
| Mixed-signal system for performing Taylor series function approximations | ||
| Brian Remy, Houston, Tex. (US); Michael D. Bryant, Austin, Tex. (US); Benito R. Fernandez, Austin, Tex. (US); and Shouli Yan, Austin, Tex. (US) | ||
| Assigned to The Board of regents, The University of Texas System, Austin, Tex. (US) | ||
| Filed on Dec. 12, 2007, as Appl. No. 11/955,006. | ||
| Claims priority of provisional application 60/869688, filed on Dec. 12, 2006. | ||
| Prior Publication US 2008/0140755 A1, Jun. 12, 2008 | ||
| Int. Cl. G06F 7/52 (2006.01); G06F 15/00 (2006.01) | ||
| U.S. Cl. 708—103 [708/200] | 7 Claims |
| 1. A mixed-signal system for performing Taylor series approximations, said system comprising:
a digital processor for calculating coefficients Fx, Fy, Fxx, Fxy, Fyy of a Taylor series equation and for calculating distance functions, wherein said digital processor includes a digital register
for storing a magnitude scaling factor φ(x0,y0) of said Taylor series equation;
a digital-to-analog converter (DAC) coupled to said digital processor;
a DAC control register, coupled to said DAC, for uploading a lead term F(x0,y0) of said Taylor series equation from said digital processor to said DAC;
a plurality of resistor-to-resistor (R2R) ladders coupled to said DAC;
a plurality of first-order digital registers, coupled to said R2R ladders, for controlling resistances of said R2R ladders;
a plurality of second-order digital registers, coupled to said digital processor, for uploading coefficients Fxx, Fxy, Fyy of said Taylor series equation from said digital processor to said DAC; and
an analog integrator or operational amplifier for adding outputs from said DAC and said R2R ladder to generate approximation
results for said Taylor series equation.
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