| US 7,454,017 B2 | ||
| Information processing unit | ||
| Masahiro Kaminaga, Sendai (Japan); Takashi Watanabe, Tokyo (Japan); and Takashi Endo, Tokyo (Japan) | ||
| Assigned to Renesas Technology Corp., Tokyo (Japan) | ||
| Filed on Nov. 18, 2004, as Appl. No. 10/990,977. | ||
| Claims priority of application No. 2003-387524 (JP), filed on Nov. 18, 2003; and application No. 2004-027550 (JP), filed on Feb. 04, 2004. | ||
| Prior Publication US 2005/0108498 A1, May 19, 2005 | ||
| Int. Cl. H04L 9/00 (2006.01) | ||
| U.S. Cl. 380—46 [713/174] | 26 Claims |
| 1. An information processing unit that uses two different potentials to express binary information, said information processing
unit comprising:
a memory for storing data;
an arithmetic unit for performing specified processing according to a program; and
a transform function for transforming a logical address and a physical address of the memory, said logical address being used
for arithmetic operation by the arithmetic unit, said physical address being determined from the logical address and a random
number by arithmetic operation,
wherein
said physical address of the memory, corresponding to a start address of a logical address used for arithmetic operation by
the arithmetic unit, is set at each arithmetic operation, or every time the information processing unit is started up, or
before newly performing processing including secret information, or if data in the memory is not used in processing thereafter;
and
said arithmetic unit generates a random number at each arithmetic processing or every time the information processing unit
is started up, and adds the random number to the start address of the logical address, and then sets a remainder, obtained
by dividing the result of the addition by the use capacity of the memory, as a physical address corresponding to a start address
of the logical address.
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