| US 7,453,739 B2 | ||
| Semiconductor integrated circuit adapted to output pass/fail results of internal operations | ||
| Hiroshi Nakamura, Fujisawa (Japan); Kenichi Imamiya, Tokyo (Japan); Toshio Yamamura, Yokohama (Japan); Koji Hosono, Yokohama (Japan); and Koichi Kawai, Yokohama (Japan) | ||
| Assigned to Kabushiki Kaisha Toshiba, Tokyo (Japan) | ||
| Filed on May 01, 2007, as Appl. No. 11/742,600. | ||
| Application 11/119744 is a division of application No. 10/318167, filed on Dec. 13, 2002, granted, now 7,023,741. | ||
| Application 11/742600 is a continuation of application No. 11/515005, filed on Sep. 05, 2006, granted, now 7,224,621. | ||
| Application 11/515005 is a continuation of application No. 11/119744, filed on May 03, 2005, granted, now 7,123,515. | ||
| Claims priority of application No. 2001-386596 (JP), filed on Dec. 19, 2001; and application No. 2002-311475 (JP), filed on Oct. 25, 2002. | ||
| Prior Publication US 2007/0201279 A1, Aug. 30, 2007 | ||
| Int. Cl. G11C 7/10 (2006.01) | ||
| U.S. Cl. 365—189.05 [365/185.22; 365/189.011] | 26 Claims |
| 1. A semiconductor memory device comprising:
a plurality of data cache circuits configured to hold data temporarily;
a plurality of sense latch circuits connected to the plurality of data cache circuits and configured to sense and latch data
read from a plurality of memory cells; and
a control circuit configured to perform a data transfer operation and a first operation,
wherein the data transfer operation is an operation to transfer data from the plurality of sense latch circuits to the plurality
of data cache circuits, and the first operation is an operation to latch data of a selected memory cell into a corresponding
one of the plurality of sense latch circuits, the data transfer operation being performed by inputting a first command or
a first command sequence, the first operation being performed automatically after the data transfer operation terminates,
and a first ready/busy signal goes to a busy status during the data transfer operation.
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