| US 7,453,088 B2 | ||
| Electro-optical device and manufacturing method thereof | ||
| Shunpei Yamazaki, Tokyo (Japan); Hisashi Ohtani, Kanagawa (Japan); and Setsuo Nakajima, Kanagawa (Japan) | ||
| Assigned to Semiconductor Energy Laboratory Co., Ltd., (Japan) | ||
| Filed on Jan. 18, 2007, as Appl. No. 11/654,781. | ||
| Application 11/654781 is a continuation of application No. 11/253275, filed on Oct. 18, 2005, granted, now 7,173,280. | ||
| Application 11/253275 is a continuation of application No. 10/919650, filed on Aug. 17, 2004, granted, now 6,977,393, filed on Dec. 20, 2005. | ||
| Application 10/919650 is a continuation of application No. 10/262261, filed on Oct. 01, 2002, granted, now 6,791,112, filed on Sep. 14, 2004. | ||
| Application 10/262261 is a continuation of application No. 09/441026, filed on Nov. 16, 1999, granted, now 6,512,271, filed on Jan. 28, 2003. | ||
| Claims priority of application No. 10-325719 (JP), filed on Nov. 16, 1998. | ||
| Prior Publication US 2007/0114537 A1, May 24, 2007 | ||
| Int. Cl. H01L 27/14 (2006.01) | ||
| U.S. Cl. 257—59 [257/72; 257/351; 257/408; 257/E29.137; 257/E29.269] | 20 Claims |
| 1. A semiconductor device comprising:
a semiconductor layer formed over a substrate, wherein the semiconductor layer contains a channel forming region and a drain
region with a lightly doped drain region interposed therebetween;
a first gate electrode formed adjacent to the semiconductor layer with a gate insulating film interposed therebetween; and
a second gate electrode covering a top surface and a side surface of the first gate electrode,
wherein a side surface of the second gate electrode overlaps the lightly doped drain region, and
wherein the side surface of the first gate electrode is aligned with a boundary between the channel forming region and the
lightly doped drain region.
|