| US 7,452,756 B2 | ||
| Semiconductor device and manufacturing process thereof | ||
| Mitsuru Kaneda, Tokyo (Japan); and Hideki Takahashi, Tokyo (Japan) | ||
| Assigned to Mitsubishi Denki Kabushiki Kaisha, Chiyoda-Ku, Tokyo (Japan) | ||
| Filed on Nov. 05, 2007, as Appl. No. 11/979,527. | ||
| Application 11/979527 is a division of application No. 11/163248, filed on Oct. 11, 2005, granted, now 7,326,996. | ||
| Claims priority of application No. 2005-020087 (JP), filed on Jan. 27, 2005. | ||
| Prior Publication US 2008/0064148 A1, Mar. 13, 2008 | ||
| Int. Cl. H01L 21/20 (2006.01); H01L 21/338 (2006.01); H01L 23/62 (2006.01) | ||
| U.S. Cl. 438—138 [438/140; 438/148; 257/342; 257/378; 257/474] | 6 Claims |
| 1. A process for manufacturing a semiconductor device, comprising:
providing a semiconductor substrate of a first conductivity type, having upper and lower surfaces;
forming a collector region of a second conductivity type on the lower surface of said semiconductor substrate;
forming at least one pair of isolation regions of the second conductivity type extending from the upper surface of said semiconductor
substrate to said collector layer for defining a drift region of the first conductivity type, in conjunction with said collector
region;
forming a base region of the second conductivity type adjacent the upper surface of said semiconductor substrate and within
the drift region;
forming an emitter region of the first conductivity type adjacent the upper surface of said semiconductor substrate and within
said base region;
forming a gate electrode opposing to said base region via an insulating layer; and
forming an emitter electrode on said emitter region;
polishing said collector region to have thickness in the range between 17 μm to 50 μm, after forming said gate electrode and
said emitter electrode; and
forming a collector electrode on said polished collector region.
|