US 11,818,901 B2
Integrated circuit including bipolar transistors
Philippe Boivin, Venelles (FR); Jean Jacques Fagot, Rousset (FR); Emmanuel Petitprez, Grenoble (FR); Emeline Souchier, Saint-Ismier (FR); and Olivier Weber, Grenoble (FR)
Assigned to STMicroelectronics (Rousset) SAS, Rousset (FR); and STMicroelectronics (Crolles 2) SAS, Crolles (FR)
Filed by STMicroelectronics (Rousset) SAS, Rousset (FR); and STMicroelectronics (Crolles 2) SAS, Crolles (FR)
Filed on Sep. 29, 2021, as Appl. No. 17/489,425.
Application 17/489,425 is a division of application No. 16/375,571, filed on Apr. 4, 2019, granted, now 11,152,430.
Claims priority of application No. 1853043 (FR), filed on Apr. 6, 2018.
Prior Publication US 2022/0020816 A1, Jan. 20, 2022
Int. Cl. H01L 21/8222 (2006.01); H10B 63/00 (2023.01); H10N 70/20 (2023.01); H10N 70/00 (2023.01)
CPC H10B 63/32 (2023.02) [H10N 70/231 (2023.02); H10N 70/826 (2023.02)] 19 Claims
OG exemplary drawing
 
1. A method, comprising:
forming a row of bipolar transistors having a common base, the common base being located between a plurality of first conduction regions and a second conduction region, the first conduction regions separated from one another by insulator walls, an insulating trench being in contact with the row of bipolar transistors;
forming a cavity in the insulating trench and the insulator walls, side surfaces of the first conduction regions being exposed in the cavity;
forming a spacer layer in the cavity, the spacer layer covering the exposed side surfaces of the first conduction regions and a side surface of the insulating trench in the cavity; and
filling the cavity with a conductive material; and
forming a metal layer in the cavity and on the spacer layer prior to the filling the cavity with the conductive material.