US 11,818,897 B1
Method of forming a stack of planar capacitors including capacitors with non-linear polar material and linear dielectric for common mode compensation in a memory bit-cell
Rajeev Kumar Dokania, Beaverton, OR (US); Noriyuki Sato, Hillsboro, OR (US); Tanay Gosavi, Portland, OR (US); Amrita Mathuriya, Portland, OR (US); and Sasikanth Manipatruni, Portland, OR (US)
Assigned to KEPLER COMPUTING INC., San Francisco, CA (US)
Filed by Kepler Computing Inc., San Francisco, CA (US)
Filed on Nov. 2, 2021, as Appl. No. 17/517,298.
Application 17/517,298 is a continuation of application No. 17/516,293, filed on Nov. 1, 2021.
This patent is subject to a terminal disclaimer.
Int. Cl. G11C 11/00 (2006.01); H10B 53/30 (2023.01)
CPC H10B 53/30 (2023.02) 20 Claims
OG exemplary drawing
 
1. A method comprising:
forming a first metal layer extending along an x-plane;
forming a second metal layer extending along the x-plane, wherein the second metal layer is above the first metal layer;
forming a first via extending along a y-plane, wherein the y-plane is orthogonal to the x-plane, and wherein the first via couples the first metal layer with the second metal layer;
forming a second via extending along the y-plane, wherein the second via couples the second metal layer, and wherein the second via is above the first via;
forming a first pedestal on the first metal layer, wherein the first pedestal is laterally offset from the first via;
forming a second pedestal on the second metal layer, wherein the second pedestal is laterally offset from the second via;
forming a first plate-line extending along a z-plane, wherein the z-plane is orthogonal to the x-plane and the y-plane;
forming a second plate-line extending along the z-plane;
forming a first planar stack of materials including a non-linear polar material, wherein the first planar stack of materials has a first top electrode and a first bottom electrode, wherein the non-linear polar material is between the first top electrode and the second bottom electrode, wherein the second bottom electrode is on the first pedestal, and wherein the first plate-line is on the first top electrode; and
forming a second planar stack of materials including a linear dielectric material, wherein the second planar stack of materials has a second top electrode and a second bottom electrode, wherein the linear dielectric material is between the second top electrode of the second planar stack of materials and the second bottom electrode and the second planar stack of materials, wherein the second bottom electrode is on the second pedestal, and wherein the second plate-line on the second top electrode.