US 11,818,892 B2
Semiconductor device and manufacturing method of semiconductor device
Dong Uk Lee, Icheon-si (KR); and Hae Chang Yang, Icheon-si (KR)
Assigned to SK hynix Inc., Icheon-si (KR)
Filed by SK hynix Inc., Icheon-si (KR)
Filed on Jun. 17, 2022, as Appl. No. 17/843,762.
Application 17/843,762 is a continuation of application No. 16/942,389, filed on Jul. 29, 2020, granted, now 11,411,017.
Claims priority of application No. 10-2020-0025559 (KR), filed on Feb. 28, 2020.
Prior Publication US 2022/0320118 A1, Oct. 6, 2022
Int. Cl. H10B 43/35 (2023.01); H10B 41/27 (2023.01); H10B 41/35 (2023.01); H10B 43/27 (2023.01)
CPC H10B 43/35 (2023.02) [H10B 41/27 (2023.02); H10B 41/35 (2023.02); H10B 43/27 (2023.02)] 10 Claims
OG exemplary drawing
 
1. A semiconductor device comprising:
a stack structure including gate patterns and insulating patterns;
a channel layer penetrating the stack structure;
a source layer spaced apart from the stack structure;
a conductor spaced apart from the stack structure;
a first select transistor between the stack structure and the source layer; and
a second select transistor between the stack structure and the conductor,
wherein the first select transistor includes:
a first carbon layer in contact with the source layer and the channel layer;
a first select gate spaced apart from the first carbon layer; and
a first gate insulating layer between the first select gate and the first carbon layer, and
wherein the second select transistor includes:
a second carbon layer in contact with the conductor and the channel layer;
a second select gate spaced apart from the second carbon layer; and
a second gate insulating layer between the second select gate and the second carbon layer.