US 11,818,890 B2
Semiconductor memory device
Go Oike, Mie (JP); and Tsuyoshi Sugisaki, Yokkaichi (JP)
Assigned to KIOXIA CORPORATION, Tokyo (JP)
Filed by KIOXIA CORPORATION, Tokyo (JP)
Filed on Feb. 7, 2022, as Appl. No. 17/665,979.
Application 17/665,979 is a continuation of application No. 17/087,724, filed on Nov. 3, 2020, granted, now 11,282,858.
Application 17/087,724 is a continuation of application No. 16/751,293, filed on Jan. 24, 2020, granted, now 10,861,875, issued on Dec. 8, 2020.
Application 16/751,293 is a continuation of application No. 16/118,598, filed on Aug. 31, 2018, granted, now 10,763,277, issued on Sep. 1, 2020.
Claims priority of application No. 2018-046940 (JP), filed on Mar. 14, 2018.
Prior Publication US 2022/0157851 A1, May 19, 2022
This patent is subject to a terminal disclaimer.
Int. Cl. H10B 43/27 (2023.01); G11C 5/06 (2006.01); G11C 16/04 (2006.01); G11C 16/08 (2006.01); H10B 41/10 (2023.01); H10B 41/27 (2023.01); H10B 41/35 (2023.01); H10B 43/10 (2023.01); H10B 43/35 (2023.01); H01L 29/792 (2006.01)
CPC H10B 43/27 (2023.02) [G11C 5/063 (2013.01); G11C 16/0483 (2013.01); G11C 16/08 (2013.01); H10B 41/10 (2023.02); H10B 41/27 (2023.02); H10B 41/35 (2023.02); H10B 43/10 (2023.02); H10B 43/35 (2023.02); H01L 29/792 (2013.01)] 12 Claims
OG exemplary drawing
 
1. A semiconductor memory device comprising:
a plurality of first conductive layers stacked in a first direction and disposed between nearest of two first slits in a second direction;
a second conductive layer disposed above the plurality of first conductive layers and disposed between one of the nearest two first slits and a second slit;
a third conductive layer disposed above the plurality of first conductive layers and disposed between another of the nearest two first slits and the second slit;
a first pillar extending through the plurality of first conductive layers and the second conductive layer in the first direction, the first pillar including a semiconductor layer;
a second pillar extending through the plurality of first conductive layers and the third conductive layer in the first direction, the second pillar including a semiconductor layer;
a first plug extending in the first direction and in contact with the second conductive layer;
a second plug extending in the first direction and in contact with the third conductive layer;
a third plug extending through the plurality of first conductive layers and the second conductive layer in the first direction and electrically connected to the first plug; and
a fourth plug extending through the plurality of first conductive layers and the third conductive layer in the first direction and electrically connected to the second plug.