| CPC H10B 43/27 (2023.02) [H01L 23/5226 (2013.01); H10B 41/27 (2023.02)] | 20 Claims |
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1. A vertical memory device, comprising:
a substrate including a cell region, a through via region on two opposite sides of the cell region, and a mold region surrounding the cell region and the through via region, the through via region being between the cell region and the mold region;
a gate electrode structure including gate electrodes on the substrate, the gate electrodes being stacked to be spaced apart from each other along a first direction substantially vertical to an upper surface of the substrate, and each of the gate electrodes extending in a second direction substantially parallel to the upper surface of the substrate and including a metal, the through via region being insulated from the gate electrode structure;
a channel extending in the first direction on the cell region of the substrate, and extending through at least a portion of the gate electrode structure; and
a first mold including first and second layers alternately and repeatedly stacked along the first direction on the mold region of the substrate, the first and second layers including different insulation materials from each other, and each of the first layers of the first mold being at a same height as and contacting a corresponding one of the gate electrodes of the gate electrode structure.
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