US 11,818,883 B2
Read only memory
Abderrezak Marzaki, Aix en Provence (FR); Mathieu Lisart, Aix en Provence (FR); and Benoit Froment, Grenoble (FR)
Assigned to STMicroelectronics (Crolles 2) SAS, Crolles (FR); and STMicroelectronics (Rousset) SAS, Rousset (FR)
Filed by STMicroelectronics (Crolles 2) SAS, Crolles (FR); and STMicroelectronics (Rousset) SAS, Rousset (FR)
Filed on Dec. 1, 2021, as Appl. No. 17/540,029.
Claims priority of application No. 2013741 (FR), filed on Dec. 18, 2020.
Prior Publication US 2022/0199632 A1, Jun. 23, 2022
Int. Cl. H10B 20/00 (2023.01); H01L 23/00 (2006.01); G11C 16/04 (2006.01)
CPC H10B 20/367 (2023.02) [G11C 16/0466 (2013.01); H01L 23/57 (2013.01)] 20 Claims
OG exemplary drawing
 
1. A memory comprising:
memory cells of a first type disposed over a first semiconductor layer of a substrate, the first type being an embedded Select in Trench Memory (eSTM) type memory cell, one of the eSTM type memory cells comprising a select transistor, the select transistor comprising a vertical trench extending to a second semiconductor layer below the first semiconductor layer; and
memory cells of a second type disposed over the first semiconductor layer, each of the memory cells of the second type comprising only one or more transistors, the first type of memory cell being a different type of memory cell than the second type of memory cell.