US 11,818,881 B2
Sub word-line driver circuit of semiconductor memory device and semiconductor memory device including the same
Kyoungmin Kim, Namyangju-si (KR); Donggeon Kim, Suwon-si (KR); Myeongsik Ryu, Anyang-si (KR); Sangwook Park, Hwaseong-si (KR); Inseok Baek, Suwon-si (KR); and Bokyeon Won, Namyangju-si (KR)
Assigned to Samsung Electronics Co., Ltd.
Filed by SAMSUNG ELECTRONICS CO., LTD., Suwon-si (KR)
Filed on Mar. 31, 2022, as Appl. No. 17/709,971.
Claims priority of application No. 10-2021-0144382 (KR), filed on Oct. 27, 2021.
Prior Publication US 2023/0130345 A1, Apr. 27, 2023
Int. Cl. G11C 11/40 (2006.01); H10B 12/00 (2023.01); H01L 25/065 (2023.01); G11C 11/408 (2006.01); H01L 29/423 (2006.01); H01L 23/498 (2006.01)
CPC H10B 12/50 (2023.02) [G11C 11/4085 (2013.01); H01L 25/0652 (2013.01); H01L 29/4238 (2013.01); H01L 23/49816 (2013.01); H01L 23/49833 (2013.01); H01L 2225/06513 (2013.01); H01L 2225/06541 (2013.01)] 20 Claims
OG exemplary drawing
 
1. A semiconductor memory device comprising:
a first sub word-line driver including a first transistor configured to supply a negative voltage to a first word-line extending in a first direction in response to a driving signal; and
a second sub word-line driver including a second transistor configured to supply the negative voltage to a second word-line extending in the first direction in response to the driving signal,
wherein the first transistor and the second transistor comprise:
a first active pattern that extends in a second direction crossing the first direction and that is connected with the first word-line through a first direct contact;
a second active pattern that extends in the second direction, that is spaced apart from the first active pattern in the second direction by a first gap and that is connected with the second word-line through a second direct contact; and
a gate pattern on a portion of the first active pattern and a portion of the second active pattern, the gate pattern partially overlapping the first active pattern and the second active pattern,
wherein the first active pattern is connected with a third direct contact that does not overlap the gate pattern and that supplies the negative voltage, and
wherein the second active pattern is connected with a fourth direct contact that does not overlap the gate pattern and that supplies the negative voltage.