US 11,818,874 B2
Method and device for finFET SRAM
Yong Li, Shanghai (CN)
Assigned to Semiconductor Manufacturing International (Shanghai) Corporation, Shanghai (CN); and Semiconductor Manufacturing International (Beijing) Corporation, Beijing (CN)
Filed by Semiconductor Manufacturing International (Shanghai) Corporation, Shanghai (CN); and Semiconductor Manufacturing International (Beijing) Corporation, Beijing (CN)
Filed on Dec. 9, 2021, as Appl. No. 17/643,504.
Application 17/643,504 is a division of application No. 15/473,205, filed on Mar. 29, 2017, granted, now 11,227,867.
Claims priority of application No. 201610379443.5 (CN), filed on Jun. 1, 2016.
Prior Publication US 2022/0102361 A1, Mar. 31, 2022
Int. Cl. H01L 29/10 (2006.01); H10B 10/00 (2023.01); H01L 21/8238 (2006.01); H01L 27/092 (2006.01); H01L 29/49 (2006.01)
CPC H10B 10/12 (2023.02) [H01L 21/823821 (2013.01); H01L 21/823842 (2013.01); H01L 21/823892 (2013.01); H01L 27/0924 (2013.01); H01L 27/0928 (2013.01); H01L 29/1083 (2013.01); H01L 29/4966 (2013.01)] 9 Claims
OG exemplary drawing
 
1. A method for manufacturing a semiconductor device, the method comprising:
providing a substrate structure including a substrate, forming an interlayer dielectric layer on the substrate, forming a plurality of trenches in the interlayer dielectric layer exposing a surface of the substrate and comprising at least a first trench for forming a gate structure of a first transistor, a second trench for forming a gate structure of a second transistor, and a third trench for forming a gate structure of a third transistor;
performing a first doping into the substrate to form a first doped region in the substrate below a bottom of the first trench, the first doped region comprising an N-type dopant;
performing a second doping into the substrate to form a second doped region in the substrate below a bottom of the second trench, the second doped region comprising a first P-type dopant;
performing a third doping into the substrate to form a third doped region in the substrate below a bottom of the third trench, the third doped region comprising a second P-type dopant;
forming an interface layer on the bottom of the plurality of trenches;
forming a high-k dielectric layer on the interface layer and sidewalls of the plurality of trenches;
forming a first PMOS work function adjustment layer on the high-k dielectric layer of the third trench;
forming a second PMOS work function adjustment layer in the plurality of trenches after forming the first PMOS work function adjustment layer;
forming an NMOS work function adjustment layer in the plurality of trenches after forming the second PMOS work function adjustment layer; and
forming a barrier layer in the plurality of trenches after forming the NMOS work function adjustment layer, and forming a metal gate layer on the barrier layer.