US 11,818,843 B2
Electronic device including interposer
Jungsik Park, Suwon-si (KR); and Soyoung Lee, Gwacheon-si (KR)
Assigned to Samsung Electronics Co., Ltd., Suwon-si (KR)
Filed by Samsung Electronics Co., Ltd., Suwon-si (KR)
Filed on Oct. 21, 2022, as Appl. No. 17/971,146.
Application 17/971,146 is a continuation of application No. 17/185,283, filed on Feb. 25, 2021, granted, now 11,483,930.
Application 17/185,283 is a continuation of application No. 16/887,585, filed on May 29, 2020, granted, now 10,939,552, issued on Mar. 2, 2021.
Application 16/887,585 is a continuation of application No. 16/121,085, filed on Sep. 4, 2018, granted, now 10,674,607, issued on Jun. 2, 2020.
Claims priority of application No. 10-2017-0116517 (KR), filed on Sep. 12, 2017.
Prior Publication US 2023/0043331 A1, Feb. 9, 2023
Int. Cl. H05K 1/14 (2006.01); G06F 1/16 (2006.01); H01Q 1/52 (2006.01); H04M 1/02 (2006.01); H04B 1/3883 (2015.01); G06F 1/20 (2006.01); G06F 1/26 (2006.01); H01Q 9/04 (2006.01); H01R 12/53 (2011.01); H05K 1/11 (2006.01); H01Q 9/42 (2006.01); H01Q 1/24 (2006.01); H01Q 21/06 (2006.01); H05K 1/02 (2006.01); H05K 1/18 (2006.01)
CPC H05K 1/144 (2013.01) [G06F 1/1626 (2013.01); G06F 1/1635 (2013.01); G06F 1/1656 (2013.01); G06F 1/1658 (2013.01); G06F 1/1698 (2013.01); G06F 1/203 (2013.01); G06F 1/263 (2013.01); H01Q 1/526 (2013.01); H01Q 9/0407 (2013.01); H01R 12/53 (2013.01); H04B 1/3883 (2013.01); H04M 1/026 (2013.01); H04M 1/0262 (2013.01); H04M 1/0277 (2013.01); H05K 1/116 (2013.01); H01Q 1/243 (2013.01); H01Q 9/42 (2013.01); H01Q 21/065 (2013.01); H05K 1/0216 (2013.01); H05K 1/147 (2013.01); H05K 1/181 (2013.01); H05K 2201/042 (2013.01); H05K 2201/10037 (2013.01); H05K 2201/10098 (2013.01); H05K 2201/10189 (2013.01); H05K 2201/10371 (2013.01); H05K 2201/10378 (2013.01)] 13 Claims
OG exemplary drawing
 
1. An electronic device comprising:
a first circuit board including an application processor disposed thereon;
a second circuit board including a first communication processor and an antenna disposed thereon; and
an interposer comprising:
a first surface and a second surface connected with the first circuit board and the second circuit board, respectively, an inner space being formed by the first circuit board, the second circuit board, and a side wall of the interposer between the first surface and the second surface,
a via, a first ending portion and a second ending portion of the via being exposed via the first surface and the second surface, respectively,
a first plating member comprising:
a first portion formed on the first surface and connected with the first ending portion of the via;
a second portion formed on the second surface and connected with the second ending portion of the via; and
a third portion continuously extended from the first portion and the second portion and covering an entire height of a portion of an outer surface of the side wall of the interposer,
a second plating member formed on a portion of the outer surface of the side wall, and
a third plating member formed on a portion of an inner surface of the side wall opposite to an area of the outer surface, between the first plating member and the second plating member, having no plating member.