| CPC H04N 25/705 (2023.01) [H04N 25/745 (2023.01)] | 20 Claims |
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1. An image sensor comprising:
a demodulation clock generation circuit configured to generate first to fourth demodulation clock signals respectively having first to fourth phases;
a demodulation phase selection circuit configured to generate first to fourth pre-demodulation signals based on the first to fourth demodulation clock signals and a random number that changes for each of a plurality of packets;
a delay circuit configured to generate a plurality of first delay signals by delaying the first pre-demodulation signal by a plurality of delay phases, a plurality of second delay signals by delaying the second pre-demodulation signal by the plurality of delay phases, a plurality of third delay signals by delaying the third pre-demodulation signal by the plurality of delay phases, and a plurality of fourth delay signals by delaying the fourth pre-demodulation signal by the plurality of delay phases; and
a phase mixer configured to generate a plurality of first demodulation signals of which phases are changed based on an address that changes for each of the plurality of packets, a plurality of second demodulation signals of which phases are changed based on the address, a plurality of third demodulation signals of which phases are changed based on the address, and a plurality of fourth demodulation signals of which phases are changed based on the address,
wherein the first to fourth phases have a phase difference of 90° from each other.
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