US 11,818,376 B2
Memory system
Daisuke Yashima, Tachikawa (JP); Masato Sumiyoshi, Yokohama (JP); Keiri Nakanishi, Kawasaki (JP); Takashi Miura, Yokohama (JP); Kohei Oikawa, Kawasaki (JP); Sho Kodama, Kawasaki (JP); Youhei Fukazawa, Kawasaki (JP); and Zheye Wang, Kawasaki (JP)
Assigned to Kioxia Corporation, Tokyo (JP)
Filed by Kioxia Corporation, Tokyo (JP)
Filed on Jul. 19, 2022, as Appl. No. 17/868,597.
Application 17/868,597 is a division of application No. 17/019,941, filed on Sep. 14, 2020, granted, now 11,431,995.
Claims priority of application No. 2020-042839 (JP), filed on Mar. 12, 2020.
Prior Publication US 2022/0353519 A1, Nov. 3, 2022
Int. Cl. H04N 19/423 (2014.01); H04N 19/146 (2014.01); H04N 19/13 (2014.01); H04N 19/184 (2014.01)
CPC H04N 19/423 (2014.11) [H04N 19/13 (2014.11); H04N 19/146 (2014.11); H04N 19/184 (2014.11)] 25 Claims
OG exemplary drawing
 
1. A memory system comprising:
an encoding unit, implemented by circuitry, configured to:
assign, using a table in which a plurality of entries each including a symbol and a frequency value associated with the symbol are arranged in a first order, codewords to symbols, respectively, according to the first order, the symbols being included in the plurality of entries, respectively; and
convert one or more input first symbols into one or more first codewords, respectively;
a frequency value update unit, implemented by the circuitry, configured to add a first value to each of one or more first frequency values that are associated with the one or more input first symbols, respectively, in one or more entries in the table that include the one or more input first symbols, respectively;
a first intra-group rearranging unit, implemented by the circuitry, configured to rearrange, after the first value is added to each of the one or more first frequency values, first entries in the table that are obtained by excluding a highest second entry and a lowest third entry from fourth entries in the table that belong to a first group, by using frequency values in the first entries;
a second intra-group rearranging unit, implemented by the circuitry, configured to rearrange, after the first value is added to each of the one or more first frequency values, fifth entries in the table that are obtained by excluding a highest sixth entry and a lowest seventh entry from eighth entries in the table that belong to a second group lower in the table than the first group, by using frequency values in the fifth entries;
an inter-group rearranging unit, implemented by the circuitry, configured to rearrange the third entry and the sixth entry in the table when a frequency value in the third entry is smaller than a frequency value in the sixth entry; and
a routing unit, implemented by the circuitry, configured to:
exchange the sixth entry for a lowest entry of the rearranged first entries and exchange the third entry for a highest entry of the rearranged fifth entries, when the third entry and the sixth entry are rearranged; and
exchange the third entry for the lowest entry of the rearranged first entries and exchange the sixth entry for the highest entry in the rearranged fifth entries, when the third entry and the sixth entry are not rearranged,
wherein the encoding unit is configured to:
assign the codewords to the symbols, respectively, according to a second order in which the plurality of entries are arranged in the table that is updated by the frequency value update unit, the first intra-group rearranging unit, the second intra-group rearranging unit, the inter-group rearranging unit, and the routing unit; and
convert one or more second symbols, which are input following the one or more input first symbols, into one or more second codewords, respectively.