US 11,818,355 B2
Video coding apparatus and video decoding apparatus
Tomohiro Ikai, Sakai (JP); Tomoko Aono, Sakai (JP); Takeshi Chujoh, Sakai (JP); Yukinobu Yasugi, Sakai (JP); and Eiichi Sasaki, Sakai (JP)
Assigned to SHARP KABUSHIKI KAISHA, Sakai (JP)
Appl. No. 17/429,024
Filed by Sharp Kabushiki Kaisha, Sakai (JP)
PCT Filed Feb. 7, 2020, PCT No. PCT/JP2020/004869
§ 371(c)(1), (2) Date Aug. 6, 2021,
PCT Pub. No. WO2020/162609, PCT Pub. Date Aug. 13, 2020.
Claims priority of application No. 2019-021630 (JP), filed on Feb. 8, 2019; and application No. 2019-057031 (JP), filed on Mar. 25, 2019.
Prior Publication US 2022/0182631 A1, Jun. 9, 2022
Int. Cl. H04N 19/13 (2014.01); H04N 19/174 (2014.01); H04N 19/70 (2014.01)
CPC H04N 19/13 (2014.11) [H04N 19/174 (2014.11); H04N 19/70 (2014.11)] 4 Claims
OG exemplary drawing
 
1. A video decoding apparatus for decoding a picture, the video decoding apparatus comprising:
a header decoding circuit that decodes an enabled flag indicating whether a synchronization process for a Context-Adaptive Binary Arithmetic Coding (CABAC) is performed for a first Coding Tree Unit (CTU) of a CTU row, in a parameter set, wherein
the header decoding circuit:
derives a raster scan CTU address list by using a tile position by raster scan of a tile in a slice,
derives a CTU address by using the raster scan CTU address list, and
derives a number of entry points by using the CTU address in a case that a value of the enabled flag is equal to 1.