US 11,818,240 B2
PAM-4 Baud-rate clock and data recovery circuit using stochastic phase detection technique
Ha Ram Ju, Seoul (KR); Sung Ho Lee, Seoul (KR); and Deog Kyoon Jeong, Seoul (KR)
Assigned to Korea Electronics Technology Institute, Seongnam-si (KR); and Seoul National University R&DB Foundation, Seoul (KR)
Filed by Korea Electronics Technology Institute, Seongnam-si (KR); and Seoul National University R&DB Foundation, Seoul (KR)
Filed on Dec. 10, 2021, as Appl. No. 17/547,378.
Claims priority of application No. 10-2020-0173015 (KR), filed on Dec. 11, 2020.
Prior Publication US 2022/0190999 A1, Jun. 16, 2022
Int. Cl. H04L 7/02 (2006.01); H04L 7/00 (2006.01); H03L 7/091 (2006.01)
CPC H04L 7/0016 (2013.01) [H03L 7/091 (2013.01); H04L 7/0054 (2013.01); H04L 7/0079 (2013.01)] 19 Claims
OG exemplary drawing
 
1. A clock and data recovery device comprising:
circuitry comprising:
an input unit through which data is inputted;
a clock input unit through which a clock is inputted;
a sampling processor configured to sample the inputted data by using the inputted clock;
a controller configured to combine results of sampling at a plurality of sampling points, to determine a state of the clock based on the combined results, and to generate a control value for controlling the clock; and
an adjustment processor configured to adjust the clock used by the sampling processor, based on the control value generated by the controller.