CPC H04L 45/28 (2013.01) [G06F 9/505 (2013.01); G06F 9/546 (2013.01); G06F 12/0862 (2013.01); G06F 12/1036 (2013.01); G06F 12/1063 (2013.01); G06F 13/14 (2013.01); G06F 13/16 (2013.01); G06F 13/1642 (2013.01); G06F 13/1673 (2013.01); G06F 13/1689 (2013.01); G06F 13/385 (2013.01); G06F 13/4022 (2013.01); G06F 13/4068 (2013.01); G06F 13/4221 (2013.01); G06F 15/17331 (2013.01); H04L 1/0083 (2013.01); H04L 43/0876 (2013.01); H04L 43/10 (2013.01); H04L 45/021 (2013.01); H04L 45/028 (2013.01); H04L 45/122 (2013.01); H04L 45/123 (2013.01); H04L 45/125 (2013.01); H04L 45/16 (2013.01); H04L 45/20 (2013.01); H04L 45/22 (2013.01); H04L 45/24 (2013.01); H04L 45/38 (2013.01); H04L 45/42 (2013.01); H04L 45/46 (2013.01); H04L 45/566 (2013.01); H04L 45/70 (2013.01); H04L 45/745 (2013.01); H04L 45/7453 (2013.01); H04L 47/11 (2013.01); H04L 47/12 (2013.01); H04L 47/122 (2013.01); H04L 47/18 (2013.01); H04L 47/20 (2013.01); H04L 47/22 (2013.01); H04L 47/24 (2013.01); H04L 47/2441 (2013.01); H04L 47/2466 (2013.01); H04L 47/2483 (2013.01); H04L 47/30 (2013.01); H04L 47/32 (2013.01); H04L 47/323 (2013.01); H04L 47/34 (2013.01); H04L 47/39 (2013.01); H04L 47/52 (2013.01); H04L 47/621 (2013.01); H04L 47/626 (2013.01); H04L 47/629 (2013.01); H04L 47/6235 (2013.01); H04L 47/6275 (2013.01); H04L 47/76 (2013.01); H04L 47/762 (2013.01); H04L 47/781 (2013.01); H04L 47/80 (2013.01); H04L 49/101 (2013.01); H04L 49/15 (2013.01); H04L 49/30 (2013.01); H04L 49/3009 (2013.01); H04L 49/3018 (2013.01); H04L 49/3027 (2013.01); H04L 49/90 (2013.01); H04L 49/9005 (2013.01); H04L 49/9021 (2013.01); H04L 49/9036 (2013.01); H04L 49/9047 (2013.01); H04L 67/1097 (2013.01); H04L 69/22 (2013.01); H04L 69/40 (2013.01); G06F 2212/50 (2013.01); G06F 2213/0026 (2013.01); G06F 2213/3808 (2013.01); H04L 69/28 (2013.01)] | 21 Claims |
1. A switch device, comprising:
an input buffer to store received packets;
an input header queue coupled to the input buffer and to:
store headers of the received packets;
generate a request corresponding to a respective received packet toward an output port based on a header of the received packet, wherein the header is stored in the input header queue; and
send the request toward the output port via a request crossbar dedicated for transferring a request, wherein a crossbar is a structure for transferring a piece of information within the switch device;
an output buffer to:
store outgoing packets to be transmitted via a respective output port; and
generate credits for granting requests based on space available in the output buffer;
a credit crossbar dedicated for transferring the credits to the input header queue;
a grant crossbar dedicated for transferring a grant corresponding to a request associated with a packet to the input header queue; and
a data crossbar dedicated for transferring the packet from the input buffer to the output buffer in response to the request being granted.
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