US 11,817,879 B2
FPGA-based rate-adaptive spatially-coupled LDPC codes for optical communications
Ivan B. Djordjevic, Tucson, AZ (US); and Xiaole Sun, Tucson, AZ (US)
Assigned to Arizona Board of Regents on Behalf of the University of Arizona, Tucson, AZ (US)
Appl. No. 17/621,639
Filed by Arizona Board of Regents on Behalf of the University of Arizona, Tucson, AZ (US)
PCT Filed Jun. 26, 2020, PCT No. PCT/US2020/039960
§ 371(c)(1), (2) Date Dec. 21, 2021,
PCT Pub. No. WO2020/264401, PCT Pub. Date Dec. 30, 2020.
Claims priority of provisional application 62/868,642, filed on Jun. 28, 2019.
Prior Publication US 2022/0360281 A1, Nov. 10, 2022
Int. Cl. H03M 13/00 (2006.01); H03M 13/11 (2006.01)
CPC H03M 13/116 (2013.01) [H03M 13/1154 (2013.01); H03M 13/616 (2013.01)] 21 Claims
OG exemplary drawing
 
1. A method for generating spatially-coupled low-density parity- check (SC-LDPC) codes, comprising:
generating one or more quasi-cyclic low-density parity-check (QC-LDPC) codes, where the one or more QC-LDPC codes are represented by one or more parity-check matrices;
assigning at least one of the generated one or more QC-LDPC codes as one or more template codes;
copying at least a portion of the one or more template codes to introduce irregularity therein; and
shifting the one or more template codes within a SC-LDPC code matrix on a sub-block basis to generate at least one SC-LDPC code.