CPC H03M 13/114 (2013.01) [H03M 13/1102 (2013.01); H03M 13/3707 (2013.01); H03M 13/3715 (2013.01); H03M 13/6502 (2013.01); H03M 13/6561 (2013.01); H04L 12/2874 (2013.01); H03M 13/1108 (2013.01); H03M 13/1117 (2013.01); H04L 2012/6478 (2013.01); H04L 2012/6489 (2013.01)] | 29 Claims |
1. A multi-channel decoder circuit, comprising:
a distributed decoder circuit comprising a set of unit decoder circuits, each unit decoder circuit configured to receive one or more codewords of a plurality of codewords associated with a plurality of input channels, and iteratively decode the one or more codewords, a number of iterations being based on a latency target; and
a distribution controller circuit configured to distribute an incoming codeword of the one or more codewords to the respective unit decoder circuit of the set of unit decoder circuits within the distributed decoder circuit, based on a predefined condition, the predefined condition relating to a quality-of-service (QoS) class of the incoming codeword, the plurality of codewords being distributed based on determining a currently available unit decoder circuit within the set of unit decoder circuits and based on the respective QoS class, a particular codeword being distributed specifically to the currently available unit decoder circuit based on a particular QoS class for the particular codeword.
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