US 11,817,864 B2
Timing system including a master device and at least a slave device synchronized with each other and related synchronization method
Luigi Sole, Milan (IT); and Antonio Giordano, Milan (IT)
Assigned to STMicroelectronics S.r.l., Agrate Brianza (IT)
Filed by STMicroelectronics S.r.l., Agrate Brianza (IT)
Filed on Jun. 14, 2022, as Appl. No. 17/839,813.
Claims priority of application No. 102021000016841 (IT), filed on Jun. 28, 2021.
Prior Publication US 2022/0416794 A1, Dec. 29, 2022
Int. Cl. H03L 7/099 (2006.01); G06F 1/08 (2006.01); G06F 1/12 (2006.01)
CPC H03L 7/099 (2013.01) [G06F 1/08 (2013.01); G06F 1/12 (2013.01)] 19 Claims
OG exemplary drawing
 
1. A timing system comprising:
a master timing device comprising:
a master oscillator stage configured to:
receive a reference signal; and
generate a first main clock signal frequency-locked with the reference signal;
a master timing stage comprising a master counter configured to update a value with a timing that depends on the first main clock signal, the master timing stage configured to generate a first local clock signal of a pulsed type, a timing of pulses of the first local clock signal being controllable by the master counter; and
a master synchronization stage configured to generate a synchronization signal synchronous with the first local clock signal, wherein the synchronization signal includes a corresponding pulse for each group of consecutive pulses of the first local clock signal formed by a number (N) of pulses; and
a slave timing device comprising:
a slave oscillator stage configured to:
receive the reference signal; and
generate a second main clock signal frequency-locked with the reference signal;
a slave timing stage comprising a slave counter configured to update a value with a timing that depends on the second main clock signal, the slave timing stage configured to generate a second local clock signal of a pulsed type, the timing of the pulses of the second local clock signal being controllable by the slave counter; and
a slave synchronization stage configured to:
read, with a timing that depends on the synchronization signal, the value of the slave counter;
compare the read value with an expected value; and
tune the value of the slave counter according to the outcome of the comparison so as to phase-lock the first and second local dock signals.