CPC H03K 5/01 (2013.01) [H03K 5/003 (2013.01); H03K 5/05 (2013.01); H03K 5/24 (2013.01)] | 20 Claims |
1. A receiver comprising:
a differential signal generator configured to receive a single-ended signal, and generate differential signals having a positive signal and a negative signal complementary to the positive signal based on the single-ended signal, a reference signal, and a pair of compensation signals;
a positive charging circuit configured to charge a first node to a power level in a logic low period of a clock signal;
a negative charging circuit configured to charge a second node to the power level in the logic low period of the clock signal;
a positive discharging circuit configured to discharge the first node according to a signal level of the positive signal in a logic high period of the clock signal;
a negative discharging circuit configured to discharge the second node according to a signal level of the negative signal in the logic high period of the clock signal;
a comparator configured to compare a signal level of the first node and a signal level of the second node and output an offset detection signal of the differential signals in response to a result of the comparison; and
an offset compensator configured to output the reference signal and the pair of compensation signals, each adjusted based on the offset detection signal obtained from the comparator, to the differential signal generator.
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