US 11,817,783 B2
Controlling reverse current in switched mode power supplies to achieve zero voltage switching
James Sigamani, Pasig (PH); and Jonathan Ross B. Fauni, Quezon (PH)
Assigned to Astec International Limited, Kowloon (HK)
Filed by Astec International Limited, Kowloon (HK)
Filed on Feb. 4, 2022, as Appl. No. 17/592,806.
Application 17/592,806 is a continuation of application No. 16/916,613, filed on Jun. 30, 2020, granted, now 11,251,705.
Prior Publication US 2022/0158557 A1, May 19, 2022
This patent is subject to a terminal disclaimer.
Int. Cl. H02M 3/158 (2006.01); H02M 1/00 (2006.01); H02M 3/335 (2006.01)
CPC H02M 3/158 (2013.01) [H02M 1/0058 (2021.05); H02M 1/007 (2021.05); H02M 1/0043 (2021.05); H02M 1/0083 (2021.05); H02M 3/33569 (2013.01)] 19 Claims
OG exemplary drawing
 
12. A method of controlling a switched mode power supply for powering a load, the method comprising:
generating, via a control circuit coupled to first and second buck circuits of a power converter, a first control signal for a power switch of the first buck circuit and a second control signal for a power switch of the second buck circuit to control the first and second buck circuits in a continuous conduction mode so that a reverse current flows in the first and second buck circuits; and
adjusting a switching frequency of the first and second control signals to control an amount of the reverse current flowing in the first and second buck circuits to achieve zero voltage switching of the power switches of the first and second buck circuits while the power converter is in its continuous conduction mode; and
wherein generating the first and second control signals comprises:
generating the first control signal and the second control signal to have overlapping on times in response to a duty cycle of the first control signal and the second control signal exceeding a duty cycle threshold value; and
generating the first control signal and the second control signal to have non-overlapping on times in response to the duty cycle of the first control signal and the second control signal being below the duty cycle threshold value.