US 11,817,772 B2
Glitch immune non-overlap operation of transistors in a switching regulator
Subhash Sahni, Dehradun (IN); Murugesh Subramaniam, Bengaluru (IN); and Pranav Sinha, Bengaluru (IN)
Assigned to TEXAS INSTRUMENTS INCORPORATED, Dallas, TX (US)
Filed by TEXAS INSTRUMENTS INCORPORATED, Dallas, TX (US)
Filed on Jul. 20, 2021, as Appl. No. 17/380,135.
Application 17/380,135 is a continuation of application No. 16/589,799, filed on Oct. 1, 2019, granted, now 11,101,726.
Prior Publication US 2021/0351688 A1, Nov. 11, 2021
This patent is subject to a terminal disclaimer.
Int. Cl. H02M 1/08 (2006.01); H03K 17/284 (2006.01); H03K 17/08 (2006.01); H02M 3/157 (2006.01); H02M 3/158 (2006.01); H02M 1/38 (2007.01); H03K 19/20 (2006.01)
CPC H02M 1/08 (2013.01) [H02M 1/38 (2013.01); H02M 3/157 (2013.01); H02M 3/158 (2013.01); H03K 17/08 (2013.01); H03K 17/284 (2013.01); H03K 19/20 (2013.01); H03K 2017/0806 (2013.01)] 16 Claims
OG exemplary drawing
 
1. A circuit, comprising:
a first gate control circuit including a first time delay element, a first logic gate, and a second logic gate, the first time delay element including an output, and wherein the first logic gate includes a first output and the second logic gate includes a second output;
a second gate control circuit including a second time delay element, a third logic gate, and a fourth logic gate, wherein the second time delay element includes an input coupled to the output of the first time delay element, the second time delay element includes an output, the third logic gate includes a third output, and the fourth logic gate includes a fourth output;
a first gate driver coupled to one of the first or third outputs;
a first selection circuit coupled to the first and third outputs;
a second gate driver coupled to one of the second or fourth outputs; and
a second selection circuit coupled to the second and fourth outputs.