US 11,817,493 B2
Semiconductor device
Mari Saji, Nagaokakyo (JP); Atsushi Kurokawa, Nagaokakyo (JP); and Koshi Himeda, Nagaokakyo (JP)
Assigned to Murata Manufacturing Co., Ltd., Kyoto-fu (JP)
Filed by Murata Manufacturing Co., Ltd., Kyoto-fu (JP)
Filed on Dec. 8, 2021, as Appl. No. 17/545,973.
Claims priority of application No. 2020-204469 (JP), filed on Dec. 9, 2020.
Prior Publication US 2022/0181470 A1, Jun. 9, 2022
Int. Cl. H01L 29/737 (2006.01); H01L 23/00 (2006.01); H01L 29/66 (2006.01)
CPC H01L 29/737 (2013.01) [H01L 24/13 (2013.01); H01L 29/66242 (2013.01); H01L 29/66318 (2013.01); H01L 2224/0401 (2013.01)] 20 Claims
OG exemplary drawing
 
1. A semiconductor device comprising:
a substrate;
a plurality of first transistors each including a mesa structure configured of a semiconductor arranged on an upper surface, which is one surface of the substrate;
a first bump which is arranged at a position overlapping the plurality of first transistors in plan view, has a shape elongated in one direction in plan view, and is connected to the plurality of first transistors;
a second bump which is arranged so as to have a space with respect to the first bump in a direction orthogonal to a longitudinal direction of the first bump; and
a first metal pattern which is arranged between the first bump and the second bump in plan view, wherein
when the upper surface of the substrate is taken as a height reference, a center of the first metal pattern in a thickness direction has a height higher than an upper surface of the mesa structure included in each of the plurality of first transistors and lower than a lower surface of the first bump.