US 11,817,471 B2
Imaging device and electronic device configured by bonding a plurality of semiconductor substrates
Hajime Yamagishi, Kanagawa (JP); Shota Hida, Nagasaki (JP); and Yuusaku Kobayashi, Nagasaki (JP)
Assigned to Sony Semiconductor Solutions Corporation, Kanagawa (JP)
Filed by SONY SEMICONDUCTOR SOLUTIONS CORPORATION, Kanagawa (JP)
Filed on Aug. 27, 2021, as Appl. No. 17/459,873.
Application 17/459,873 is a continuation of application No. 16/614,955, granted, now 11,133,343, previously published as PCT/JP2018/017477, filed on May 2, 2018.
Claims priority of application No. 2017-104991 (JP), filed on May 26, 2017.
Prior Publication US 2021/0391371 A1, Dec. 16, 2021
This patent is subject to a terminal disclaimer.
Int. Cl. H01L 27/146 (2006.01)
CPC H01L 27/14634 (2013.01) [H01L 27/14636 (2013.01)] 20 Claims
OG exemplary drawing
 
1. An imaging device, comprising:
a first chip including:
a first semiconductor substrate including a photoelectric conversion region that converts incident light into an electric charge; and
a first insulating layer including a first multilayer wiring electrically connected to the photoelectric conversion region, wherein the first multilayer wiring includes a first vertical signal line (VSL1) to output a first pixel signal based on the electric charge; and
a second chip including:
a second semiconductor substrate including a plurality of transistors;
a third semiconductor substrate; and
a second insulating layer including a second multilayer wiring electrically connected to the plurality of transistors, wherein the second multilayer wiring includes a first wiring that is connected to a second wiring in the third semiconductor substrate through a conductive via, and wherein the first wiring, the second wiring and the conductive via are located in a peripheral portion of the first chip.