US 11,817,470 B2
Stacked substrate structure with inter-tier interconnection
Jeng-Shyan Lin, Tainan (TW); Dun-Nian Yaung, Taipei (TW); Jen-Cheng Liu, Hsin-Chu (TW); Hsun-Ying Huang, Tainan (TW); Wei-Chih Weng, Tainan (TW); and Yu-Yang Shen, Kaohsiung (TW)
Assigned to Taiwan Semiconductor Manufacturing Company, Ltd., Hsinchu (TW)
Filed by Taiwan Semiconductor Manufacturing Company, Ltd., Hsin-Chu (TW)
Filed on Jun. 16, 2021, as Appl. No. 17/349,120.
Application 17/349,120 is a continuation of application No. 16/167,810, filed on Oct. 23, 2018, granted, now 11,043,522.
Application 16/167,810 is a continuation of application No. 15/365,064, filed on Nov. 30, 2016, granted, now 10,121,812, issued on Nov. 6, 2018.
Claims priority of provisional application 62/272,128, filed on Dec. 29, 2015.
Prior Publication US 2021/0313376 A1, Oct. 7, 2021
Int. Cl. H01L 27/146 (2006.01); H01L 23/48 (2006.01); H01L 23/00 (2006.01); H01L 23/528 (2006.01); H01L 25/065 (2023.01); H01L 25/00 (2006.01); H01L 23/532 (2006.01); H01L 21/768 (2006.01); H01L 21/78 (2006.01)
CPC H01L 27/14634 (2013.01) [H01L 21/76898 (2013.01); H01L 21/78 (2013.01); H01L 23/481 (2013.01); H01L 23/5283 (2013.01); H01L 24/00 (2013.01); H01L 25/0657 (2013.01); H01L 25/50 (2013.01); H01L 27/1463 (2013.01); H01L 27/1469 (2013.01); H01L 27/14636 (2013.01); H01L 23/53223 (2013.01); H01L 23/53238 (2013.01); H01L 23/53266 (2013.01); H01L 23/53295 (2013.01); H01L 2224/80895 (2013.01); H01L 2224/80896 (2013.01)] 20 Claims
OG exemplary drawing
 
1. An integrated chip structure, comprising:
a first plurality of interconnects within a first dielectric structure on a first substrate;
a second plurality of interconnects within a second dielectric structure on a second substrate;
a bonding structure arranged between the first dielectric structure and a surface of the second substrate facing the bonding structure; and
an inter-tier interconnect structure extending between the first plurality of interconnects and the second plurality of interconnects and through the second substrate, wherein the inter-tier interconnect structure comprises a first region extending through the second substrate and a second region surrounded by the bonding structure, the second region having a trapezoidal shape with tapered sidewalls and contacting a lower surface of the first region that faces the first substrate.