CPC H01L 27/14634 (2013.01) [H01L 21/76898 (2013.01); H01L 21/78 (2013.01); H01L 23/481 (2013.01); H01L 23/5283 (2013.01); H01L 24/00 (2013.01); H01L 25/0657 (2013.01); H01L 25/50 (2013.01); H01L 27/1463 (2013.01); H01L 27/1469 (2013.01); H01L 27/14636 (2013.01); H01L 23/53223 (2013.01); H01L 23/53238 (2013.01); H01L 23/53266 (2013.01); H01L 23/53295 (2013.01); H01L 2224/80895 (2013.01); H01L 2224/80896 (2013.01)] | 20 Claims |
1. An integrated chip structure, comprising:
a first plurality of interconnects within a first dielectric structure on a first substrate;
a second plurality of interconnects within a second dielectric structure on a second substrate;
a bonding structure arranged between the first dielectric structure and a surface of the second substrate facing the bonding structure; and
an inter-tier interconnect structure extending between the first plurality of interconnects and the second plurality of interconnects and through the second substrate, wherein the inter-tier interconnect structure comprises a first region extending through the second substrate and a second region surrounded by the bonding structure, the second region having a trapezoidal shape with tapered sidewalls and contacting a lower surface of the first region that faces the first substrate.
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