US 11,817,428 B2
Memory device
Masayoshi Tagami, Kuwana (JP); Ryota Katsumata, Yokkaichi (JP); Jun Iijima, Yokkaichi (JP); Tetsuya Shimizu, Yokkaichi (JP); Takamasa Usui, Yokkaichi (JP); and Genki Fujita, Yokkaichi (JP)
Assigned to KIOXIA CORPORATION, Tokyo (JP)
Filed by KIOXIA CORPORATION, Tokyo (JP)
Filed on Feb. 1, 2022, as Appl. No. 17/590,373.
Application 17/590,373 is a continuation of application No. 16/916,979, filed on Jun. 30, 2020, granted, now 11,270,980.
Application 16/916,979 is a continuation of application No. 16/390,639, filed on Apr. 22, 2019, granted, now 10,741,527, issued on Aug. 11, 2020.
Application 16/390,639 is a continuation of application No. 15/706,017, filed on Sep. 15, 2017, granted, now 10,297,578, issued on May 21, 2019.
Claims priority of application No. 2017-042675 (JP), filed on Mar. 7, 2017.
Prior Publication US 2022/0157784 A1, May 19, 2022
Int. Cl. H01L 29/788 (2006.01); H01L 25/065 (2023.01); H01L 25/00 (2006.01); H01L 23/00 (2006.01); H10B 41/10 (2023.01); H10B 41/27 (2023.01); H10B 43/10 (2023.01); H10B 43/27 (2023.01); H10B 43/35 (2023.01); H10B 43/40 (2023.01); H10B 43/50 (2023.01)
CPC H01L 25/0657 (2013.01) [H01L 24/08 (2013.01); H01L 25/50 (2013.01); H10B 41/10 (2023.02); H10B 41/27 (2023.02); H10B 43/10 (2023.02); H10B 43/27 (2023.02); H10B 43/35 (2023.02); H10B 43/40 (2023.02); H10B 43/50 (2023.02); H01L 24/05 (2013.01); H01L 2224/0401 (2013.01); H01L 2224/05025 (2013.01); H01L 2224/05147 (2013.01); H01L 2224/05571 (2013.01); H01L 2224/08146 (2013.01); H01L 2225/06544 (2013.01); H01L 2225/06565 (2013.01)] 8 Claims
OG exemplary drawing
 
1. A memory device comprising:
a first memory cell array including a first stacked body, the first stacked body including a plurality of first electrode layers each extending in a first direction; and
a peripheral circuit facing the first memory cell array and driving the first memory cell array, the peripheral circuit and the first memory cell array being arranged in a second direction, the second direction crossing the first direction, the plurality of first electrode layers being stacked in the second direction, wherein
the plurality of first electrode layers each has a length along the first direction such that a first-first electrode layer of the plurality of first electric layers has a length shorter than a length of a second-first electrode layer of the plurality of first electric layers, and
the first-first electrode layer is positioned between the peripheral circuit and the second-first electrode layer.