US 11,817,407 B2
Molded semiconductor package with high voltage isolation
Shao Ping Wan, Singapore (SG); Eric Brion Acquitan, Singapore (SG); Dexter Reynoso, Singapore (SG); Jürgen Schredl, Mering (DE); and Woon Yik Yong, Singapore (SG)
Assigned to Infineon Technologies AG, Neubiberg (DE)
Filed by Infineon Technologies AG, Neubiberg (DE)
Filed on May 17, 2022, as Appl. No. 17/746,306.
Application 17/746,306 is a continuation of application No. 17/113,170, filed on Dec. 7, 2020, granted, now 11,355,460.
Prior Publication US 2022/0278060 A1, Sep. 1, 2022
This patent is subject to a terminal disclaimer.
Int. Cl. H01L 23/00 (2006.01); H01L 23/31 (2006.01); H01L 21/56 (2006.01)
CPC H01L 24/05 (2013.01) [H01L 21/565 (2013.01); H01L 23/3142 (2013.01); H01L 24/45 (2013.01); H01L 24/85 (2013.01); H01L 2224/0569 (2013.01); H01L 2924/301 (2013.01)] 21 Claims
OG exemplary drawing
 
1. A molded semiconductor package, comprising:
a first semiconductor die attached to a first substrate, the first semiconductor die comprising a first bond pad at a first side of the first semiconductor die which faces away from the first substrate and an insulating layer covering the first side;
an electrical conductor attached to a part of the first bond pad exposed by an opening in the insulating layer;
a mold compound encasing the first semiconductor die; and
an electrically insulative material filling the opening in the insulating layer and sealing the part of the first bond pad exposed by the opening in the insulating layer,
wherein the electrically insulative material separates the mold compound from the part of the first bond pad exposed by the opening in the insulating layer.