US 11,817,406 B2
Semiconductor die employing repurposed seed layer for forming additional signal paths to back end-of-line (BEOL) structure, and related integrated circuit (IC) packages and fabrication methods
Yue Li, San Diego, CA (US); Durodami Lisk, San Diego, CA (US); and Jinying Sun, San Diego, CA (US)
Assigned to QUALCOMM INCORPORATED, San Diego, CA (US)
Filed by QUALCOMM Incorporated, San Diego, CA (US)
Filed on Sep. 23, 2021, as Appl. No. 17/483,325.
Prior Publication US 2023/0090181 A1, Mar. 23, 2023
Int. Cl. H01L 25/065 (2023.01); H01L 23/00 (2006.01)
CPC H01L 24/05 (2013.01) [H01L 24/03 (2013.01); H01L 24/11 (2013.01); H01L 24/13 (2013.01); H01L 24/16 (2013.01); H01L 25/0655 (2013.01); H01L 25/0657 (2013.01); H01L 2224/0231 (2013.01); H01L 2224/02331 (2013.01); H01L 2224/0401 (2013.01); H01L 2224/05082 (2013.01); H01L 2224/16146 (2013.01); H01L 2224/16227 (2013.01); H01L 2225/0652 (2013.01); H01L 2225/06517 (2013.01)] 29 Claims
OG exemplary drawing
 
1. An integrated circuit (IC) package, comprising:
a die, comprising:
a back end-of-line (BEOL) interconnect structure;
a plurality of under bump metallization (UBM) interconnects each coupled to the BEOL interconnect structure, the plurality of UBM interconnects comprising:
a first UBM interconnect; and
a second UBM interconnect that does not have a coupled interconnect bump; and
a raised interconnect bump coupled to the first UBM interconnect;
wherein the die further comprises:
a seed layer coupling the first UBM interconnect to the second UBM interconnect, to couple the raised interconnect bump to the second UBM interconnect;
wherein the BEOL interconnect structure comprises a metallization layer comprising:
a plurality of first metal interconnects comprising a plurality of metal pads, each of the plurality of first metal interconnects coupled to a UBM interconnect among the plurality of UBM interconnects; and
a second metal interconnect coupled to the second UBM interconnect.