US 11,817,404 B2
Post passivation interconnect
Yi-An Lin, Hsinchu (TW); Alan Kuo, Hsinchu (TW); C. C. Chang, Hsinchu (TW); and Yu-Lung Shih, Hsinchu (TW)
Assigned to TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD., Hsinchu (TW)
Filed by TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD., Hsinchu (TW)
Filed on Aug. 5, 2021, as Appl. No. 17/395,216.
Application 16/658,243 is a division of application No. 15/582,955, filed on May 1, 2017, granted, now 10,453,811.
Application 17/395,216 is a continuation of application No. 16/658,243, filed on Oct. 21, 2019, granted, now 11,114,395.
Claims priority of provisional application 62/427,786, filed on Nov. 29, 2016.
Prior Publication US 2021/0375802 A1, Dec. 2, 2021
This patent is subject to a terminal disclaimer.
Int. Cl. H01L 23/00 (2006.01); H01L 23/525 (2006.01); H01L 21/768 (2006.01); H01L 23/528 (2006.01)
CPC H01L 24/02 (2013.01) [H01L 23/525 (2013.01); H01L 23/5283 (2013.01); H01L 21/76885 (2013.01); H01L 2224/024 (2013.01); H01L 2224/0235 (2013.01); H01L 2224/0239 (2013.01); H01L 2224/02313 (2013.01); H01L 2224/02317 (2013.01); H01L 2224/02351 (2013.01); H01L 2224/02373 (2013.01); H01L 2224/0401 (2013.01); H01L 2224/05008 (2013.01); H01L 2224/05541 (2013.01); H01L 2224/131 (2013.01); H01L 2224/13024 (2013.01); H01L 2224/13147 (2013.01); H01L 2924/01013 (2013.01); H01L 2924/01029 (2013.01); H01L 2924/01074 (2013.01); H01L 2924/01079 (2013.01); H01L 2924/05042 (2013.01); H01L 2924/14 (2013.01); H01L 2924/3511 (2013.01)] 20 Claims
OG exemplary drawing
 
1. An integrated circuit (IC) device comprising:
a redistribution line over a substrate, wherein an entire sidewall of the redistribution line is curved;
a passivation layer over the redistribution line, wherein a distance from a bottommost surface of the passivation layer to the substrate is less than a distance from a bottommost surface of the redistribution line to the substrate; and
a polymer layer over the passivation layer.