US 11,817,387 B2
Semiconductor device including dummy patterns and peripheral interconnection patterns at the same level
Jang-Gn Yun, Hwaseong-si (KR); Jaesun Yun, Anyang-si (KR); and Joon-Sung Lim, Yongin-si (KR)
Assigned to SAMSUNG ELECTRONICS CO., LTD., Suwon-si (KR)
Filed by SAMSUNG ELECTRONICS CO., LTD., Suwon-si (KR)
Filed on May 23, 2022, as Appl. No. 17/750,481.
Application 17/750,481 is a continuation of application No. 17/060,179, filed on Oct. 1, 2020, granted, now 11,342,263.
Application 17/060,179 is a continuation of application No. 16/151,526, filed on Oct. 4, 2018, granted, now 10,796,991, issued on Oct. 6, 2020.
Application 16/151,526 is a continuation of application No. 14/957,113, filed on Dec. 2, 2015, granted, now 10,115,667, issued on Oct. 30, 2018.
Claims priority of application No. 10-2014-0172283 (KR), filed on Dec. 3, 2014.
Prior Publication US 2022/0285262 A1, Sep. 8, 2022
Int. Cl. H10B 43/40 (2023.01); H01L 23/528 (2006.01); H01L 23/31 (2006.01); H01L 27/06 (2006.01); H01L 23/522 (2006.01); H10B 43/27 (2023.01)
CPC H01L 23/528 (2013.01) [H01L 23/3192 (2013.01); H01L 23/522 (2013.01); H01L 27/0688 (2013.01); H10B 43/40 (2023.02); H01L 2924/0002 (2013.01); H10B 43/27 (2023.02)] 20 Claims
OG exemplary drawing
 
1. A semiconductor device, comprising:
a semiconductor substrate;
a first pattern on the semiconductor substrate;
a second pattern disposed at substantially the same level as the first pattern and spaced apart from the first pattern;
a peripheral circuit on the semiconductor substrate, at least a portion of the peripheral circuit being between the semiconductor substrate and the first pattern;
a dummy interconnection structure on the semiconductor substrate;
a stacked structure including cell gate conductive patterns on the first pattern, the cell gate conductive patterns being stacked while being spaced apart from each other in a vertical direction perpendicular to an upper surface of the first pattern;
a cell vertical structure disposed on the first pattern and passing through the cell gate conductive patterns, wherein at least one side of the stacked structure has a staircase shape; and
a dummy contact plug directly on and contacting the second pattern,
wherein a portion of the cell vertical structure directly contacts the first pattern,
wherein an upper end of the dummy contact plug is at a higher level than an uppermost cell gate conductive pattern among the cell gate conductive patterns,
wherein a lower end of the dummy contact plug is at a lower level than a lowermost cell gate conductive pattern among the cell gate conductive patterns,
wherein the dummy interconnection structure is electrically isolated,
wherein the dummy interconnection structure includes dummy patterns disposed at different levels from each other with respect to an upper surface of the semiconductor substrate,
wherein the dummy patterns include:
a first dummy pattern; and
a second dummy pattern disposed at a higher than the first dummy pattern,
wherein the peripheral circuit includes:
a first peripheral interconnection pattern disposed at substantially the same level as the first dummy pattern; and
a second peripheral interconnection pattern disposed at substantially the same level as the second dummy pattern.