US 11,817,378 B2
Apparatus and method for providing a scalable ball grid array (BGA) assignment and a PCB circuit trace breakout pattern for RF chip interfaces
Nelly Chen, San Diego, CA (US); Gary Yao Zhang, San Diego, CA (US); Michael Randy May, San Jose, CA (US); Shrinivas Gopalan Uppili, San Diego, CA (US); and Varin Sriboonlue, San Diego, CA (US)
Assigned to QUALCOMM INCORPORATED, San Diego, CA (US)
Filed by QUALCOMM INCORPORATED, San Diego, CA (US)
Filed on Jun. 30, 2021, as Appl. No. 17/364,220.
Claims priority of provisional application 63/049,530, filed on Jul. 8, 2020.
Prior Publication US 2022/0013442 A1, Jan. 13, 2022
Int. Cl. H05K 1/02 (2006.01); H01L 23/498 (2006.01); H01L 23/66 (2006.01); H05K 3/34 (2006.01)
CPC H01L 23/49816 (2013.01) [H01L 23/66 (2013.01); H05K 1/0228 (2013.01); H05K 3/3436 (2013.01); H01L 2223/6605 (2013.01); H05K 2201/09227 (2013.01); H05K 2201/10098 (2013.01); H05K 2201/10734 (2013.01)] 30 Claims
OG exemplary drawing
 
1. An apparatus, comprising:
a first semiconductor die stacked vertically relative to a layer of a printed circuit board (PCB), the first semiconductor die coupled to the PCB with a ball grid array (BGA);
a second semiconductor die stacked vertically relative to the layer of the PCB, the second semiconductor die coupled to the PCB with a BGA;
a pin map corresponding to each BGA and covering a surface area of the PCB, the pin map comprising a plurality of electrical designations for each pin in the pin map and a plurality of empty spaces within the pin map; each electrical designation of the plurality of electrical designations on the pin map comprising one of a positive polarity (P+), a negative polarity (P−), or an electrical ground (G);
each pin map including a first repeating pin polarity pattern; the first repeating pin polarity pattern comprising a lane unit tile, the lane unit tile having a central region defined by four pin map units, two of the four pin map units comprising two pins corresponding to a signal lane within the PCB.