US 11,817,359 B2
Warp mitigation using pattern-matched metal layers in organic substrates
Hien Dang, Nanuet, NY (US); and Sri M. Sri-Jayantha, Ossining, NY (US)
Assigned to International Business Machines Corporation, Armonk, NY (US)
Filed by International Business Machines Corporation, Armonk, NY (US)
Filed on Sep. 1, 2020, as Appl. No. 17/009,006.
Prior Publication US 2022/0068735 A1, Mar. 3, 2022
Int. Cl. H01L 23/14 (2006.01); H01L 21/48 (2006.01); G06F 30/392 (2020.01); H01L 21/027 (2006.01); H01L 23/498 (2006.01); G06F 30/398 (2020.01)
CPC H01L 23/145 (2013.01) [G06F 30/392 (2020.01); G06F 30/398 (2020.01); H01L 21/027 (2013.01); H01L 21/4857 (2013.01); H01L 23/49822 (2013.01); H01L 23/49838 (2013.01); H01L 23/49894 (2013.01)] 19 Claims
OG exemplary drawing
 
1. An organic substrate comprising:
one or more layers made of non-conductive material, each of the layers having one or more tile subareas, one or more of the layers being an upper layer on an upper side of a flat reference plane and one or more of the layers being a lower layer on a lower side of the flat reference plane;
one or more corresponding layer pairs, each corresponding layer pair having one of the upper layers, being a corresponding upper layer, and one of the lower layers, being a corresponding lower layer, where the corresponding upper layer and the corresponding lower layer are equidistant from and symmetric about the flat reference plane;
one or more corresponding tile subareas, each of the corresponding tile subareas having an upper tile subareas in the corresponding upper layer, being a corresponding upper tile subarea, and a lower tile subareas in the corresponding lower area, being a corresponding lower tile subarea, where the corresponding upper tile subarea and the corresponding lower tile subarea are in a same vertical projection;
a symmetric upper layout made of a conductive material disposed on one of the corresponding upper tile subareas, the symmetric upper layouts having one or more upper portions that have no electrical function being non-electrically functioning upper portions; and
a symmetric lower layout made of the conductive material disposed on the respective corresponding lower tile subarea, the symmetric lower layouts having one or more lower portions that have no electrical function, being non-electrically functioning lower portions, the non-electrically functioning lower portions having one or more of the lower non-electrically functioning portions,
wherein the lower non-electrically functioning portions are equal in shape with a logical intersection of an aggregate of extracted lower major features from the respective corresponding lower tile subarea and an aggregate of extracted upper major features in the corresponding upper tile subarea, and
wherein the conductive material in the symmetric upper layout and the symmetric lower layout, respectively, are equal in surface area within a tolerance and are vertical projections of one another.