US 11,817,355 B2
Semiconductor device
Hu Wang, Shanghai (CN); Shan Shan Wang, Shanghai (CN); Feng Qiu, Shanghai (CN); and Wei Hu Zhang, Shanghai (CN)
Assigned to Semiconductor Manufacturing International (Shanghai) Corporation, Shanghai (CN); and Semiconductor Manufacturing International (Beijing) Corporation, Beijing (CN)
Filed by Semiconductor Manufacturing International (Shanghai) Corporation, Shanghai (CN); and Semiconductor Manufacturing International (Beijing) Corporation, Beijing (CN)
Filed on Oct. 11, 2021, as Appl. No. 17/450,483.
Application 17/450,483 is a division of application No. 16/930,878, filed on Jul. 16, 2020, granted, now 11,201,088.
Claims priority of application No. 201910645338.5 (CN), filed on Jul. 17, 2019.
Prior Publication US 2022/0028746 A1, Jan. 27, 2022
Int. Cl. H01L 29/66 (2006.01); H01L 29/78 (2006.01); H01L 29/10 (2006.01); H01L 21/8234 (2006.01); H01L 29/423 (2006.01); H01L 21/02 (2006.01); H01L 27/088 (2006.01); H01L 21/311 (2006.01); H01L 21/3213 (2006.01)
CPC H01L 21/823462 (2013.01) [H01L 21/02271 (2013.01); H01L 21/31111 (2013.01); H01L 21/31116 (2013.01); H01L 21/32135 (2013.01); H01L 21/823425 (2013.01); H01L 21/823437 (2013.01); H01L 27/088 (2013.01); H01L 29/1095 (2013.01); H01L 29/42368 (2013.01); H01L 29/66681 (2013.01); H01L 29/7816 (2013.01)] 8 Claims
OG exemplary drawing
 
1. A semiconductor device, comprising:
a substrate;
a gate structure, located over the substrate, the gate structure including a first gate oxide layer, a second gate oxide layer, and a silicon layer, wherein:
the first gate oxide layer is over the substrate, and the first gate oxide layer has a sloped sidewall on one side and a vertical sidewall on another side, the first gate oxide layer including silicon oxide, and the sloped sidewall of the first gate oxide layer being covered by a by-product produced by an anisotropic dry etching using an etching gas with high fluorocarbon ratio;
the second gate oxide layer is over the substrate and on the sloped sidewall of the first gate oxide layer, and a thickness of the second gate oxide layer is less than a thickness of the first gate oxide layer, the second gate oxide layer including silicon oxide; and
the silicon layer is formed over the first gate oxide layer and the second gate oxide layer.