US 11,817,345 B2
Multiple thickness semiconductor-on-insulator field effect transistors and methods of forming the same
Gulbagh Singh, Tainan (TW); Po-Jen Wang, Taichung (TW); and Kun-Tsang Chuang, Miaoli (TW)
Assigned to Taiwan Semiconductor Manufacturing Company Limited, Hsinchu (TW)
Filed by Taiwan Semiconductor Manufacturing Company Limited, Hsinchu (TW)
Filed on Jun. 27, 2022, as Appl. No. 17/849,765.
Application 17/849,765 is a continuation of application No. 16/885,377, filed on May 28, 2020, granted, now 11,398,403.
Prior Publication US 2022/0328345 A1, Oct. 13, 2022
Int. Cl. H01L 21/762 (2006.01); H01L 27/12 (2006.01); H01L 29/06 (2006.01); H01L 29/786 (2006.01)
CPC H01L 21/76224 (2013.01) [H01L 21/7624 (2013.01); H01L 21/76227 (2013.01); H01L 21/76229 (2013.01); H01L 21/76232 (2013.01); H01L 21/76264 (2013.01); H01L 21/76283 (2013.01); H01L 27/1233 (2013.01); H01L 29/0653 (2013.01); H01L 29/786 (2013.01); H01L 29/78696 (2013.01)] 20 Claims
OG exemplary drawing
 
1. A method of forming a semiconductor structure, comprising:
providing a substrate including a top semiconductor layer that includes a first region, a second region, and a third region;
forming at least one first diffusion barrier layer that covers a first region of the top semiconductor layer and does not cover the second region and the third region of the top semiconductor layer;
thinning the second region and the third region of the top semiconductor layer without thinning the first region of the top semiconductor layer;
forming a second diffusion barrier layer that covers the first region and the second region of the top semiconductor layer and does not cover the third region of the top semiconductor layer;
additionally thinning the third region of the top semiconductor layer while a combination of the at least one first diffusion barrier layer and the second diffusion barrier layer masks the first region and the second region of the top semiconductor layer;
forming shallow trenches through the top semiconductor layer after said additional thinning of the third region of the top semiconductor layer;
forming a shallow trench isolation structure by filling the shallow trenches with a dielectric fill material and recessing portions of the dielectric fill material; and
forming semiconductor devices on discrete semiconductor portions in the first region and in the second region.