US 11,817,315 B2
Zincblende structure group III-nitride
David John Wallis, Cambridge (GB); Martin Frentrup, Cambridge (GB); Menno Johannes Kappers, Cambridge (GB); and Suman-Lata Sahonta, Cambridge (GB)
Assigned to Cambridge Enterprise Limited, Cambridge (GB); and Anvil Semiconductors Limited, Warwickshire (GB)
Filed by Cambridge Enterprise Limited, Cambridge (GB); and Anvil Semiconductors Limited, Allesley (GB)
Filed on Feb. 25, 2022, as Appl. No. 17/681,607.
Application 17/681,607 is a continuation of application No. 16/496,388, granted, now 11,302,530, previously published as PCT/EP2018/058250, filed on Mar. 29, 2018.
Claims priority of application No. PCT/EP2017/057764 (WO), filed on Mar. 31, 2017.
Prior Publication US 2022/0384181 A1, Dec. 1, 2022
Int. Cl. H01L 33/00 (2010.01); H01L 33/32 (2010.01); H01L 21/02 (2006.01); H01L 29/04 (2006.01); H01L 29/20 (2006.01)
CPC H01L 21/0254 (2013.01) [H01L 21/0262 (2013.01); H01L 21/02381 (2013.01); H01L 21/02447 (2013.01); H01L 21/02458 (2013.01); H01L 29/04 (2013.01); H01L 29/2003 (2013.01); H01L 33/007 (2013.01); H01L 33/32 (2013.01)] 9 Claims
OG exemplary drawing
 
1. A method of manufacturing a semiconductor structure comprising a substantially (001) oriented zincblende structure group III-N layer, the method including the steps:
providing a silicon substrate;
providing a 3C—SiC layer on the silicon substrate;
subjecting the 3C—SiC layer to a nitridation step at a temperature T1 in the range 800-1100° C.;
growing a zincblende structure group III-N nucleation layer at a temperature T2 in the range 550-650° C. with a growth rate in the range 0.1-1 nm/s to a thickness in the range 10-100 nm;
carrying out a nucleation layer recrystallization step at a temperature T3 in the range 850-920° C.; and
depositing and growing the zincblende structure group III-N layer by MOVPE at temperature T3 in the range 850-920° C., to a thickness of at least 0.3 μm, wherein the group III-nitride layer is a In·sub·xAl·sub·yGa·sub·1-x-yN based layer, where 0≤x≤1, 0≤y≤1.