US 11,817,175 B2
Enable signal generation circuit and semiconductor apparatus using the same
Mino Kim, Icheon-si (KR); and Hyeong Soo Jeong, Icheon-si (KR)
Assigned to SK hynix Inc., Icheon-si (KR)
Filed by SK hynix Inc., Icheon-si (KR)
Filed on May 2, 2022, as Appl. No. 17/734,893.
Application 17/734,893 is a continuation of application No. 17/187,260, filed on Feb. 26, 2021, granted, now 11,348,625.
Application 17/187,260 is a continuation in part of application No. 16/730,206, filed on Dec. 30, 2019, granted, now 10,943,629, issued on Mar. 9, 2021.
Claims priority of application No. 10-2019-0065721 (KR), filed on Jun. 4, 2019.
Prior Publication US 2022/0262416 A1, Aug. 18, 2022
This patent is subject to a terminal disclaimer.
Int. Cl. G11C 8/18 (2006.01); G11C 8/10 (2006.01); G11C 7/10 (2006.01); G11C 8/04 (2006.01)
CPC G11C 8/18 (2013.01) [G11C 7/106 (2013.01); G11C 7/1063 (2013.01); G11C 7/1087 (2013.01); G11C 8/04 (2013.01); G11C 8/10 (2013.01)] 20 Claims
OG exemplary drawing
 
1. A memory device configurable to communicate with a memory controller via a plurality of buses including a command bus, a clock bus, and a data bus, the memory device comprising:
a command decoding circuit configured to generate an operation code having n bits whenever command signals are received via the command bus in synchronization with a clock signal via the clock bus; and
a repair enable signal generation circuit configured to:
trigger a generation operation of a repair enable signal when an operation code of which a mth bit has a predetermined value is received;
perform the generation operation of the repair enable signal based on a predetermined number of operation codes received immediately after triggering the generation operation of the repair enable signal; and
interrupt the generation operation of the repair enable signal when the predetermined number of operation codes, which correspond to their expected values, are not received in a required order,
wherein n is an integer equal to or greater than 3, and m is an integer between 1 and n.