CPC G11C 8/18 (2013.01) [G11C 7/106 (2013.01); G11C 7/1063 (2013.01); G11C 7/1087 (2013.01); G11C 8/04 (2013.01); G11C 8/10 (2013.01)] | 20 Claims |
1. A memory device configurable to communicate with a memory controller via a plurality of buses including a command bus, a clock bus, and a data bus, the memory device comprising:
a command decoding circuit configured to generate an operation code having n bits whenever command signals are received via the command bus in synchronization with a clock signal via the clock bus; and
a repair enable signal generation circuit configured to:
trigger a generation operation of a repair enable signal when an operation code of which a mth bit has a predetermined value is received;
perform the generation operation of the repair enable signal based on a predetermined number of operation codes received immediately after triggering the generation operation of the repair enable signal; and
interrupt the generation operation of the repair enable signal when the predetermined number of operation codes, which correspond to their expected values, are not received in a required order,
wherein n is an integer equal to or greater than 3, and m is an integer between 1 and n.
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