| CPC G11C 8/00 (2013.01) [G06F 13/1668 (2013.01); G11C 8/10 (2013.01); G11C 11/40611 (2013.01)] | 17 Claims |
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1. A semiconductor memory device comprising:
a memory cell array comprising first memory cells connected to a first word line and second memory cells connected to a second word line, the second word line being physically adjacent to the first word line;
an address input buffer configured to store a first row address addressing the first word line concentrically accessed by the first row address;
an adjacent row address generator configured to generate a second row address addressing the second word line based on the first row address;
a pre-decoder configured to select one of the first row address output from the address input buffer and the second row address output from the adjacent row address generator; and
a row decoder configured to activate a selected word line among the first word line and the second word line, the selected word line corresponding to the selected one of the first row address and the second row address,
wherein the second memory cells are refreshed when the second row address is selected.
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