US 11,817,173 B2
Timing-based computer architecture systems and methods
Advait Madhavan, Bethesda, MD (US); Matthew William Daniels, Silver Spring, MD (US); and Mark David Stiles, Silver Spring, MD (US)
Assigned to UNIVERSITY OF MARYLAND, COLLEGE PARK, College Park, MD (US); and GOVERNMENT OF THE UNITED STATES OF AMERICA, AS REPRESENTED BY THE SECRETARY OF COMMERCE, Gaithersburg, MD (US)
Filed by University of Maryland, College Park, College Park, MD (US); and THE UNITED STATES OF AMERICA AS REPRESENTED BY THE SECRETARY, DEPARTMENT OF COMMERCE, Washington, DC (US)
Filed on Oct. 1, 2021, as Appl. No. 17/492,526.
Claims priority of provisional application 63/086,453, filed on Oct. 1, 2020.
Prior Publication US 2022/0108736 A1, Apr. 7, 2022
Int. Cl. G11C 7/00 (2006.01); G11C 7/22 (2006.01); G11C 7/10 (2006.01); H03K 19/20 (2006.01); G11C 7/12 (2006.01); G06F 17/16 (2006.01); G11C 5/06 (2006.01)
CPC G11C 7/222 (2013.01) [G06F 17/16 (2013.01); G11C 5/06 (2013.01); G11C 7/1012 (2013.01); G11C 7/1069 (2013.01); G11C 7/1096 (2013.01); G11C 7/12 (2013.01); H03K 19/20 (2013.01)] 9 Claims
OG exemplary drawing
 
1. A temporal state machine comprising:
a temporal computational unit comprising at least one circuit to perform a time-domain operation;
a temporal memory unit; and
circuitry to electrically couple memory output lines and memory input lines of the temporal memory to the computational unit;
wherein the computational unit and temporal memory unit are electrically coupled such that the computation unit can access time-encoded memory recall wavefronts from the temporal memory to perform the time-domain operation, and output time-encoded output wavefronts.