US 11,817,169 B2
Memory, memory system and operation method of memory system
Munseon Jang, San Jose, CA (US); Hoiju Chung, San Jose, CA (US); and Jang Ryul Kim, San Jose, CA (US)
Assigned to SK hynix Inc., Gyeonggi-do (KR)
Filed by SK hynix Inc., Gyeonggi-do (KR)
Filed on Nov. 22, 2021, as Appl. No. 17/532,826.
Claims priority of provisional application 63/235,511, filed on Aug. 20, 2021.
Prior Publication US 2023/0056231 A1, Feb. 23, 2023
Int. Cl. G11C 29/42 (2006.01); G11C 7/10 (2006.01); G11C 29/00 (2006.01); G11C 29/12 (2006.01)
CPC G11C 29/42 (2013.01) [G11C 7/1039 (2013.01); G11C 29/1201 (2013.01); G11C 29/702 (2013.01)] 11 Claims
OG exemplary drawing
 
1. A memory system, comprising:
a memory; and
a memory controller which includes a spare buffer suitable for storing an error location in the memory and data at the location, and commands the memory to perform a spare read operation when an address of a region where a read operation needs to be performed matches with an error address stored in the spare buffer, otherwise, commands the memory to perform a normal read operation,
wherein the error address is an address of the region of the memory including the error location.