CPC G11C 29/42 (2013.01) [G11C 7/1039 (2013.01); G11C 29/1201 (2013.01); G11C 29/702 (2013.01)] | 11 Claims |
1. A memory system, comprising:
a memory; and
a memory controller which includes a spare buffer suitable for storing an error location in the memory and data at the location, and commands the memory to perform a spare read operation when an address of a region where a read operation needs to be performed matches with an error address stored in the spare buffer, otherwise, commands the memory to perform a normal read operation,
wherein the error address is an address of the region of the memory including the error location.
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