US 11,817,167 B2
Variable word length access
Elad Sity, Kfar Saba (IL); and Eliad Hillel, Kfar Saba (IL)
Assigned to NeuroBlade Ltd., Tel Aviv (IL)
Filed by NeuroBlade Ltd., Hod-Hashron (IL)
Filed on Mar. 12, 2021, as Appl. No. 17/199,599.
Application 17/199,599 is a continuation of application No. 16/783,767, filed on Feb. 6, 2020, granted, now 11,514,996.
Application 16/783,767 is a continuation of application No. PCT/IB2019/001005, filed on Sep. 6, 2019.
Application PCT/IB2019/001005 is a continuation in part of application No. 16/512,546, filed on Jul. 16, 2019, granted, now 11,269,743.
Application 16/512,546 is a continuation of application No. PCT/IB2018/000995, filed on Jul. 30, 2018.
Claims priority of provisional application 62/727,653, filed on Sep. 6, 2018.
Claims priority of provisional application 62/548,990, filed on Aug. 23, 2017.
Claims priority of provisional application 62/538,722, filed on Jul. 30, 2017.
Claims priority of provisional application 62/538,724, filed on Jul. 30, 2017.
Prior Publication US 2021/0202025 A1, Jul. 1, 2021
Int. Cl. G11C 29/38 (2006.01); G11C 11/406 (2006.01); G11C 29/36 (2006.01); G06F 11/10 (2006.01); G11C 11/408 (2006.01)
CPC G11C 29/38 (2013.01) [G06F 11/1068 (2013.01); G11C 11/4087 (2013.01); G11C 11/40618 (2013.01); G11C 29/36 (2013.01); G11C 2029/3602 (2013.01)] 35 Claims
OG exemplary drawing
 
1. An integrated circuit that comprises:
a memory unit comprising memory cells, an output port, and read circuitry; and
a processing unit;
wherein the read circuitry comprises a reduction unit and a first group of in-memory read paths for outputting up to a first number of bits through the output port;
wherein the processing unit is configured to send to the memory unit a read request for reading a second number of bits from the memory unit; and
wherein the reduction unit is configured to control the in-memory read paths, during a read operation triggered by the read request, based on the first number of bits and the second number of bits, wherein the reduction unit is configured to utilize portions of relevant in-memory read paths during the read operation and to maintain in a low power mode a sense amplifier of at least some irrelevant in-memory read paths.